{
  "schema_version": "1",
  "model": {
    "id": "mlx-community/Mixtral-8x7B-Instruct-v0.1-4bit",
    "revision": "4e8f70450ccdfa3a4b9a4133eaa0d88e43882383",
    "architecture": "mixtral",
    "quantization": {
      "group_size": 64,
      "bits": 4
    },
    "n_experts": 8,
    "top_k": 2,
    "moe_layers": 32
  },
  "strata": {
    "commit": "6562877",
    "mlx_lm": "0.31.3"
  },
  "mode": "streamed",
  "measured_on": {
    "chip": "Apple M5 Max",
    "ram_gb": 137.4,
    "os": "macOS 26.5.1",
    "mlx_lm": "0.31.3"
  },
  "workload": {
    "prompt_set": "bench/mixed-v1",
    "prompt": "Explain how a CPU pipeline works.",
    "generated_tokens": 140,
    "warmup_tokens": 40,
    "decoding": "greedy"
  },
  "memory": {
    "target_ram_gb": 16.0,
    "reserve_gb": 4.0,
    "available_gb": 12.0,
    "enforced_memory_gb": null,
    "full_footprint_gb": 26.27,
    "measured_peak_gb": 10.48,
    "peak_rss_gb": 9.82,
    "swap_growth_gb": -0.02,
    "compression_events": 0,
    "expert_budget": 2,
    "working_set_gb": 7.25,
    "mode": "paged"
  },
  "throughput": {
    "tokens_per_s": 1.97,
    "p50_ms": 528.5,
    "p95_ms": 622.0,
    "ssd_reads_mb_per_tok": 4233.1
  },
  "fidelity": {
    "method": "decode-mode teacher-forced, paged vs resident",
    "prompt_set": "arch_fidelity/mixed-v1",
    "budget": 2,
    "positions": 112,
    "agreement_pct": 100.0,
    "perplexity_delta_pct": 0.0,
    "high_confidence_flips": 0,
    "max_abs_dlogit": 0.0,
    "mean_kl": 0.0,
    "bit_exact": true
  },
  "honesty": {
    "device_real": false,
    "physical_constraint_validated": false,
    "measurement_type": "development-host benchmark",
    "memory_peak_scope": "load-through-generation",
    "throughput_is_optimistic": true
  },
  "sample_output": "A CPU pipeline is a design technique used in modern CPUs to improve performance by allowing multiple instructions to be processed simultaneously in a series of stages. Each stage in the pipeline performs a specific task on the instruction, such as fetching it from memory, decoding it, or executing it.\n\nThe pipeline is divided into several stages, which can vary depending on the CPU architecture, but typically include:\n\n1. Instruction Fetch (IF): In this stage, the CPU fetches the instruction from memory and loads it into the instruction register (IR).\n2. Instruction Decode (ID): In this stage,"
}